
Design Verification Engineer
2 weeks ago
Project description
Join a leading-edge team responsible for the verification of advanced interconnect systems in state-of-the-art microprocessors. This role focuses on ensuring the functionality, performance, and reliability of high-bandwidth data communication architectures.
Responsibilities
Develop and maintain verification environments using SystemVerilog and UVM
Perform formal verification tasks to validate design properties
Create and execute test plans for fabric and interconnect systems
Write, debug, and analyze test cases to ensure high-quality digital design
Collaborate with cross-functional teams to ensure verification aligns with design specifications
Skills
Must have
Proficiency in SystemVerilog and UVM
Experience with formal verification techniques
Strong understanding of digital design and verification processes
Knowledge of interconnect or fabric architectures
Nice to have
Familiarity with performance modeling
Background in Verilog and digital design
Experience with high-bandwidth interconnect protocols
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