
Senior Staff Engineer Digital Layout
2 weeks ago
In your new role you will:
- Be responsible for the quality of the physical design and the fulfillment of the required KPIs
- Be a key contributor working together with the physical design verification and synthesis owners to reach the timing closure and signoff criteria as planned
- Be the interface with top level, digital and analog design teams both local and from other sites to ensure a smooth integration at top
- Implement, update and improve the scripts used in the Physical Design flow
- Mentor younger Digital Layout Engineers
You are best equipped for this task if you have:
- A University Degree in Electrical Engineering, Computer Science, or a related field
- At least 4 years of experience in implementing complex SoC designs from RTL to GDS, preferred in an UNIX environment.
- Expertise in floor-planning, power, CTS, place and route and physical verification with knowledge of synthesis and timing analysis
- Skills acquired by previous usage of various CAD tools like: Innovus, ICC/ICC2, Calibre, StarRC. Primetime and Design Compiler are considered as a plus
- Knowledge of bonding diagrams generation
- Very good scripting knowledge using TCL, Python and/or Perl
- Previous experience with physical design work-packages planning (including effort estimation) and risk management
- Very good communication skills and fluency in English
Infineon
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